Welcome! As a Senior or Principal CMP PD Engineer in our Technology Development Group based in Boise, you will identify, diagnose, and resolve assembly process related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology!

Additional responsibilities include coordinating and carrying out process, equipment, and material evaluation/optimization to implement changes at process step, leading and participating in yield improvement and cost reduction activities, handling new process baseline qualifications, and managing, auditing, and collaborating closely with material suppliers to achieve quality, cost, and risk management objectives.

We are a part of a highly collaborative atmosphere, interacting with various groups such as process integration, electrical failure analysis, yield improvement, manufacturing, and equipment vendors, to ensure robust CMP processes that meet the detailed physical and electrical requirements for Micron products. You will grow into an experienced engineer, driving CMP technology roadmaps, which have a direct influence on Micron’s global leadership in semiconductor manufacturing!

Responsibilities include, but not limited to:

• Developing chemical mechanical planarization processes to meet the physical & electrical requirements of Micron’s products.
• Optimizing CMP processes to reduce cost, process variability, and improve process capability.
• Collaborating with process integration and other process development teams to develop innovative new solutions.
• Conducting root cause and failure mode analysis to understand the limitations of current hardware, CMP consumable and drive CMP development projects with OEMs and consumable vendors for solutions.
• Performing fundamental research to drive innovative solutions for next-generation products.
• Maintaining a technology development pilot manufacturing line.
• Support process transfer to production facilities (some international travel may be required).

Minimum Qualifications:

• Experience with design of experiment techniques (DOE), SPC, Defect analysis and data analysis
• Strong analytical and creative problem-solving skills.
• Ability to use extensive technical knowledge to guide strategic directions.
• Ability to resolve sophisticated issues through root-cause or model-based problem solving.
• Proficiency in statistics, preferably in statistical process control.
• Ability to work independently, with minimal direction, and a focus on meeting commitments.
• Ability to multi-task and manage numerous projects simultaneously.
• Hands on experience with CMP tools and endpoint systems.

Education and Experience:

• M.S./Ph. D. (or equivalent education) in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Chemistry, Physics, or other related technical fields.
• 3 to 5 years of semiconductor process engineering experience in CMP related process preferably in 300mm wafer fab.
• Experience in dielectrics/metals CMP PD with fundamental understanding of slurry/ pad interactions is desired.
• Experience in FEOL/ BEOL CMP process development and understanding of CMP related electrical/probe failure.
• Knowledge of semiconductor processing, solid-state device physics desirable.