The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to support high frequency clock domains, the complexity of clocking structure has increased significantly. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints.

What you'll be doing:

• Develop Clock RTL generation and distribution tools for the next generation NVIDIA projects.

• Collaborate with the Clocks, unit, post-silicon and backend teams to understand the current concerns with Clocking and come up with solutions for supporting high speed Clocking.

• Understand the physical aspects of the chip and develop better clock distribution techniques.

• Improve Power, Performance, and Area (PPA) of state-of-the-art NVIDIA GPUs and Mobile SOCs.

• Contribute to new design implementation flows.

What we need to see:

• BS or MS (preferred) degree or equivalent experience in CE or EE

• At least 3+ years of work experience.

• Validated strong coding skills in C++ or other industry-standard scripting languages.

• Deep understanding of logic optimization techniques and PPA trade-offs.

• Excellent problem solving and debugging skills.

• Strong interpersonal and collaboration skills are required.

Ways to stand out from the crowd:

• Prior experience in RTL design (Verilog), verification and synthesis.

• Proficiency in C++, Perl, Python, Make scripting.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant people in the world working for us and, due to unprecedented growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.