We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.  

Meet the Team

The CAD-IP team at Silicon Labs leads the selection, procurement and qualification of 3rd party IPs, also known as vendor IP or external IP, and sets up an IP workflow for managing the IPs, that are incorporated into SoC designs.

Responsibilities

• In charge of the acquisition, integration, characterization, release and support of all 3rd party physical and soft Intellectual Property (IP) used at Silicon Labs  

• Collaborate closely with the design teams on their design flows and be a bridge between IP vendors and Silicon Labs  

• Obtain requirements (e.g. characteristics of memory compiler, standard cells, etc. required for a specific project) from design teams and identify appropriate IP suppliers  

• Engage in evaluation and benchmarking of IPs provided by various suppliers  

• Plan, analyze, implement and maintain scalable software solutions to manage and verify EDA views from internal and external providers  

• Characterize timing, noise and power of standard-cells, IO circuits, and memory designs  

• Prioritize and accomplish the most important objectives of the organization on a committed schedule, both individually and working with others  

• Perform tool evaluations/benchmarks and report or track bugs in the software to the vendor  

Skills You Will Need

Minimum qualifications:

• Experience in physical and soft IP acquisition, installation, and support

• Deep understanding of modern digital, analog, mixed signal, power and SOC IC’s development flows and methodologies as well as typical IP needs

• Experience with EDA tools such as Virtuoso, Liberate and Crossfire

• Proficiency in  Python, PERL, Makefile, skill, TCL

The following will be considered a plus:

• Familiarity with IP collaterals such as liberty, LEF, GDS or verilog

• Familiarity with Circuit Design (Analog and Digital) concepts and simulation tools

• Proven track-record showing support for various design teams

• Excellent team work, communication and interpersonal skills with both internal teams and external vendors

Benefits & Perks 

You can look forward to the following benefits:   

• 401k plan with match and Roth plan option. 

• Equity rewards (RSUs). 

• Employee Stock Purchase Plan (ESPP). 

• Free downtown parking. 

• Hybrid work schedule 

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental & vision plans. 

• Life/AD&D and disability coverage. 

• Flexible spending accounts. 

• Adoption assistance. 

• Back-up childcare. 

• Additional benefit options (commuter benefits, legal benefits, pet insurance). 

• Flexible vacation plan 

• 3 paid volunteer days per year 

• Tuition reimbursement 

• Onsite gym 

• Wellness offerings 

The annualized base pay range for this role is expected to be between $114,428 - $212,510 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.