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Job Description

The position is with the Memory Modeling IP library R&D team within the Hardware System Verification R&D Protocol team. This Product Engineering role contributes to the successful field and customer readiness of our Hardware System Verification products and specifically interfaces with internal and external customers to explore, debug, triage, and consult on diverse problems and solutions that address their system level memory protocol and memory model struggles. This role within the Memory Model Portfolio IP team and works to resolve, disposition, and schedule repair of model defects.

• Our world class verification platforms include cycle-based emulation and FPGA-based prototyping on state-of-the-art hardware-software platforms.
• Our memory IP ranges from simple to highly complex, across a number of memory vendors, and includes families like SPI flash, SDRAM (DDRx, LPDDRx, HBMx), DFI PHY, NAND Flash, eMMC, SD Card, PSRAM and UFS.
• Our customer base is global and ranges across many industries—all using memory devices on their SoC projects. The internal team interfaces are likewise global.

As a teamer working with a sophisticated and elegant set of hardware-software platforms, tools, and supporting IP and a global, diverse, customer base, this role has career path potential to grow in any of several directions depending on interest, performance, and acquired skillset.

• As the field and customer face of our protocol IP team, this role requires an outgoing, humanistic temperament as well as excellent people skills, high emotion IQ, articulate expression of ideas, superb communication skills with diverse behavioral styles, and advanced fluency in English written and verbal expression.
• As the face of our protocol team to both internal and external experts in design level language (synthesizable RTL such as Verilog and SystemVerilog) and hardware verification by emulation, this role requires practical skills, expertise, and demonstrable experience in both domains.
• As the intermediary between user and R&D, this role requires advanced debugging and problem-solving skills that can be adapted to and applied across many, diverse protocols. Specific protocol knowledge is not required.  Experience navigating and understanding requirements, vendors, debug, and verification of complex protocols is required.
• As the point of contact with customers and their struggles, this role requires helping customers characterize the root problem they are trying to solve, even when they don’t know how to articulate it.
• As a team member and collaborator working with folks in a fast-moving industry, this role requires flexibility, adaptability, curiosity, energy, and stability with an open listening heart, sensitive gut intuition, and a “YES” brain.

If you are excited by the opportunity and challenge of bringing this hard-to-find set of qualities and behaviors to our MMP product engineering role,  you’ll relish becoming a true expert problem solver in the memory protocol domain, a true expert in verification use models within the Palladium and Protium products, and a true expert in navigating and building business oriented customer relationships.

Team

This team develops in-depth technical expertise generally, in the use of our current and next generation systems, bringing internal designs to functionality on the next generation system, and debug of the overall integrated platforms. You will also become a respected and trusted source of detailed knowledge helping to make our account teams and customers successful in their use of a complex, world class verification platform.

The position on this specific IP team offers an opportunity and the challenge of focusing in the advanced protocol and IP arena and initial career focus is exclusively on memory technologies as applied to our verification platforms.

Position

The Lead Product Engineer for Memory Model Portfolio IP content is responsible for, but not limited to:

• In this position, you will be a product engineering specialist for the Memory Model Portfolio (MMP) IP library product for all supported hardware platforms.
• You will build and manage an extensive web of ongoing relationships with external customers and internal field engineers.
• You will respond to questions and debug complex, protocol-based problems both internally and with customers to help users achieve their verification goals as they intersect with our diverse array of memory protocol IP.
• You will evaluate memory model behaviors for compliance with institutional standards and vendor datasheets.
• You will work closely with R&D to communicate findings as well as to define and schedule repairs and enhancements.
• You will help drive integration of newer memory model technologies to improve the user’s memory model bring-up time and performance during early adopter and beta situations.
• You will help create, present, and assist in deployment of internal facing and customer facing training collateral that guides users toward best practices for bringing up and testing with memory models.
• Your work will include all supported hardware platforms, current and future. Examples: Palladium Z2, Palladium Z3, Protium X2, Protium X3 and future generations.

The following is minimum REQUIRED EXPERIENCE:

• The position requires BSEE with at least 5 years of industry experience in designing hardware systems and in post-release deployment and support of hardware systems OR a MSEE with at least 2 years of experience in designing hardware systems and in post-release deployment and support of hardware systems.
• Advanced fluency in both written and spoken English with superb communication skills.
• Experience supporting, training, and negotiating with internal and external customers.
• Expert level knowledge of RTL design using languages Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
• Extensive debugging experience, including protocol based.
• Experience with team-wide collaboration tools and process.
• Drive and ability to organize and plan workload and tasks effectively.

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