Director, Firmware Engineering (PCIe)

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

The mission of this role is to lead and scale the firmware engineering organization responsible for architecting and delivering firmware and microcontroller subsystems for Astera Labs’ SoC and systems products.

As a Director of Firmware Engineering, you will own the technical vision, execution strategy, and organizational development of the firmware team. You will be responsible for delivering highly differentiated firmware capabilities that are foundational to Astera Labs’ products across networking and compute infrastructure platforms.

This is a hands-on leadership role requiring both deep technical expertise and strong people leadership. Firmware is considered equally important to hardware at Astera Labs, and this role will have significant customer visibility and cross-functional influence across silicon, systems, networking, and compute architecture teams.

Key Responsibilities

• Lead, mentor, and scale a high-performing firmware engineering team, including hiring and organizational development
• Define and drive the firmware architecture and roadmap aligned with product and company strategy across networking and compute platforms
• Partner with hardware, ASIC, and system architecture teams (including network and compute architects) to define and deliver robust HW-SW interfaces
• Oversee execution of firmware development across multiple programs, ensuring quality, scalability, and on-time delivery
• Drive customer engagement, including supporting bring-up, debugging, and feature enablement in networking and compute deployments
• Establish best practices for firmware development, validation, release processes, and CI/CD infrastructure
• Influence product direction through deep technical insight into PCIe, system architecture, and network/compute workloads
• Foster a culture of ownership, innovation, and execution excellence

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, or related field; Master’s preferred
• 12+ years of experience in firmware/software development for complex SoC/silicon products in networking and/or compute systems (server, storage, hyperscale infrastructure)
• 5+ years of experience leading and managing high-performing engineering teams
• Proven track record of delivering complex firmware systems from architecture through production
• Strong understanding of modern data center architectures spanning networking and compute domains
• Strong ability to operate at both strategic and execution levels in a fast-paced environment
• Excellent communication skills and ability to engage effectively with customers and cross-functional teams

Required Experience

• Deep expertise in PCIe (Gen5 and beyond), including debugging with analyzers and exercisers
• Strong proficiency in C/C++ and experience building firmware SDKs
• Experience with Python for automation, validation, and firmware quality
• Experience working closely with ASIC/SoC teams to define and validate HW-SW interfaces
• Familiarity with firmware development environments (gcc/Make, GitHub, CI/CD pipelines, documentation tools)
• Experience with system-level interfaces including PCIe controllers, DDR, NVMe, and AMBA/AHB
• Hands-on experience with networking and/or compute system platforms, including server or hyperscale deployments

Preferred Experience

• Experience with PAM4 SerDes and understanding of link-level behaviors (equalization, CDR, link budgets)
• Hands-on experience with PCIe-based systems in server, storage, networking, and compute environments
• Experience with AIC firmware (NICs, switches) or PCIe/Ethernet switching stacks
• Experience working with data center networking stacks or compute acceleration platforms (e.g., GPU/AI systems)
• Background in embedded firmware for high-performance connectivity products