Senior RTL to GDS Principal Application Engineer

Posted:
8/4/2024, 5:00:00 PM

Location(s):
Oregon, United States ⋅ California, United States ⋅ Austin, Texas, United States ⋅ Texas, United States ⋅ Portland, Oregon, United States ⋅ Banning, California, United States ⋅ San Jose, California, United States

Experience Level(s):
Senior

Field(s):
Software Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are excited to welcome highly talented hardware designers and application engineers to join our Cadence North America Field Applications Team. Working at Cadence means working alongside the industry’s brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the world's most powerful supercomputer to innovating in the field of artificial intelligence and machine learning.

Key Responsibilities

Provide technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff
Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
Conduct technical presentations and product demonstrations
Drive technical evaluations/benchmarks to success
Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
Drive adoption and proliferation of Cadence tools and technologies
Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements 

Job Requirements

Minimum
BS degree Computer Science/Engineering, Electrical, Engineering, or related field
8+ years of design/EDA experience
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required
Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure
Experience with advanced nodes 10nm and below
Experience in scripting languages such as Tcl/Perl/Python is a must
Strong customer-facing communication and problem-solving skills
Strong personal drive for continuous learning and expanding professional skill sets
Strong verbal, written, and customer communication skills

Preferred
MS degree Computer Science/Engineering, Electrical, Engineering, or related field
Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired
Experience with advanced nodes 5nm and below

#LI-MA1

The annual salary range for San Jose, CA is $ 120,400 to $223,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems

Website: https://www.cadence.com/

Headquarter Location: San Jose, California, United States

Employee Count: 5001-10000

Year Founded: 1988

IPO Status: Public

Industries: Aerospace ⋅ Electronic Design Automation (EDA) ⋅ Hardware ⋅ Mobile ⋅ Semiconductor ⋅ Software