Job Description

We are seeking a Technical Lead Digital Design Engineer with deep expertise in high-performance PCIE controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, CDC, lint etc.
• Utilize tools from Synopsys/Cadence for design and emulation.

Basic Qualifications:

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• 5+ years of digital design experience, with 4+ years focused on PCIE controller, PCS or PHY implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:

• Hands-on experience with PCIE Controller or Serdes/PHY IP.
• Hands-on pre-silicon and post-silicon design implementation.
• Hands-on experience  FW interaction and embedded design.
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Top level integration and DFT knowledge.

Preferred Experience:

• PCIE SerDes controller or IP level experience.
• Understanding of PAD design, DFT, and floor planning.
• Experience with NIC, switch, or storage product development including embedded FW.
• Familiarity with working in design and verification workflows in a CI/CD environment.