The role of the Silicon PCIe Bringup and Validation Engineer involves the initiation and validation of the PCIe subsystems within Rivos SOC design. This position demands a comprehensive grasp of cutting-edge PCIe design tailored for server applications, covering aspects such as physical design, logic, performance, system, and software. Responsibilities includes test generation, configuring test infrastructure, planning and executing bringup processes, and developing and executing validation plans specifically for PCIe systems. Currently, the intention is to fill technical lead or senior technical staff positions for this role.