At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities:
- Design and integration of IPs in SoC based on high-level architectural specifications from customer.
- Perfom Lint/CDC checks on the design for quality assurance and resolve issues related to the same.
- Create synthesis constraints for the disign at IP and Soc level and perform basic synthesis for PPA optimization.
- Create detailed Microarchitectural Specification Documents for the Design. 
- Provide support to verification team for test plan creation, coverage analysis and feature debug.
- Provide support to physical design team as needed for implementation of design.
- Use innovative solutions to automate repetitive tasks.
- Collaborate within and across teams for effective project execution.

Requirements:
- B.E/B.Tech/M.Tech with around 4-7 years of experience as digital design engineer.
- Good knowledge of digital design fundametals and Veriog/SV.
- Good knowledge of Lint/CDC tools and ability to create setup from scratch.
- Knowledge of creating synthesis constraints and STA. Knowledge of synthesis tool is a plus.
- Knowlege of simulation tools (Xcelium, Verisium) to support Verification.
- Experience with AMBA protocols and other ARM IPs is a plus.
- Experience with high speed IPs like PCIe, Ethernet, DDR is a plus.
- Knowledge of Scripting languages (python/Perl/Tcl).
- Ability to innovate and automate repetitive tasks
- Good communication skills for effective collaboration within and across teams.

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