Job Details:

Job Description: 

We are an end-to-end design team, based in Bangalore part of Intel Labs. We are looking for highly motivated individuals with a passion to work closely with design teams and creatively impact design flows and development. You will be responsible for the complete physical/back-end design convergence of complex SOC partitions starting from Synthesis till Tape-out. Along with the partition ownership you would be responsible for enhancing/customizing the PD flow and methodology based on the project needs. Your responsibilities will include the following: Working closely with the Design and Micro-Arch team in studying and analyzing the micro-arch specifications Develop timing constraints and provide feedback based on RTL synthesisOwn IP block level floor planning, CTS and P and R optimizations to meet design specs. Verifying and ensuring that Area/Power/Performance specifications are met. Verify design for all physical design verification flows which include STA, FEV, IR drop, Noise, Low power checks and DRC LVS Understand Intel physical design flows and debug/enhance the methodology as per project needs If required apply research-based learnings to improve design convergence

Qualifications:

You should possess a Master's degree in EE with at least 5 years of experience or a Bachelor's degree in EE with at least 7 years of experience in VLSI physical design. Additional qualifications include: Knowledge of microelectronic designs, semiconductor device physics, CMOS process and physical layout. Good understanding of complete Physical design flow.Hands-on experience in converging complex blocks from RTL to GDSII (more than 500K instances) with embedded macros and low power implementation. Experience with PCIE or LPDDR phy integration is an add-on. Tape out experience with good understanding of latest process nodes DRC's (10nm, 7m/5nm). Experience in automation for design methodology and flow development. Strong debugging skills is must and should come up with technical solutions independently. Experience in logic synthesis, timing constraint development, floorplan, power plan, CTS, routing and timing closure and DRC and LVS closure.Experience in backend verification flows like STA, FEV, IR-drop analysis and low power verification.Good hands-on knowledge on EDA tools like Synopsys FC/DC-ICC2, Primetime, Spyglass, Cadence LEC, Ansys Redhawk and Calibre Drv/ICWEBV2.Good knowledge in scripting languages like Tcl and Shell (csh/tcsh/bash). Hands-on Experience in developing utilities in TCL/TK. Familiarity with hardware description language such as Verilog or System Verilog.Must be a good team player. Efficient in working with cross functional/geo teams with strong communication and leadership skills.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence.