Posted:
11/13/2025, 1:25:41 PM
Location(s):
Hsinchu, Taiwan
Experience Level(s):
Senior
Field(s):
Product
Job Responsibilities:
Develop, validate, and deploy 3D-IC system-level design planning & physical implementation flow.
Design flow automation for 3D-IC system-level analysis & physical verification and verify simulation results.
Work closely with cross-functional teams, project managers, and customers to explore, develop and drive 3D-IC implementation, RC extraction, analysis, and verification flow enablement.
Job Requirements:
Solid working knowledge and hands-on experience in synthesis, block, or top-level physical PnR implementation, and signoff flows.
Strong programming and scripting skills in Tcl and Shell.
BS or MS degree in EE, EECS, or CE with 5 years of engineering experience in the semiconductor industry.
Excellent skills in problem-solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Independent, self-starter who can work across a worldwide organization and customer base.
Website: https://www.cadence.com/
Headquarter Location: San Jose, California, United States
Employee Count: 5001-10000
Year Founded: 1988
IPO Status: Public
Industries: Aerospace ⋅ Electronic Design Automation (EDA) ⋅ Hardware ⋅ Mobile ⋅ Semiconductor ⋅ Software