Job Details:

Job Description: 

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are
The Full Chip Timing (FCT) Design Automation team plays a critical role in supporting all aspects of full

chip timing integration. Our mission is to enable seamless timing closure and optimization across the

entire backend flow. We develop and maintain automation environments, tools, and methodologies that

ensure high-quality timing models and constraint management.

Who You Are

Some of the responsibilities of this role will include but not limited to:

• Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.

• Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.

• Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently with strong scripting expertise.

• Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on product plans such as operating conditions and binning.

• Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning and rollup generation, producing indicators for the team.

• Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

• Build and maintain automation environments for timing model generation.

• Run timing models and generate and publish indicators.

• Support backend platforms to resolve timing violations• Drive timing closure across physical design stages

• Innovate with AI-based tools, indicators, and ad-hoc automation

• Own constraint management and budgeting flows using top high end CAD tools

• Proactive, self-driven mindset with strong ownership attitude

• Customer-focused and collaborative team player

• Curious, innovative, and eager to push boundaries

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• The candidate must have a Bachelor’s Degree in Electronics, Electrical, Computer Engineering or a related field with relevant experience with 1+ years of experience in scripting and software development (TCL, Python, AI-based coding tools) -OR- Master’s Degree in Electronics/Electrical/Computer Engineering

• At least a year of experience in backend design: synthesis, place and route (P and R)

• At least a year of experience with optimization flows of STA tools

Preferred Qualifications

• 2+ years of experience in:

  • x86 CPU architecture

  • TCL/Perl/Python programming

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.