Key Responsibilities
- Seeking a highly motivated engineer for C&S group physical design team who will be responsible for physical design implementation & Signoff. Ensure quality adherence during all stages of the project life cycle.
- Will be responsible for floor planning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).
- The role would involve in-depth knowledge and responsibilities spanning all aspects of physical implementation.
- Actively work as part of team both locally & also with multi-site teams.
- Candidate will be responsible for ensuring best-in-class Power, Performance, Area and schedule.
- Need to work closely with front end and integration team to ensure successful tapeouts.
- Writing scripts in Perl and TCL to achieve productivity enhancements through automation.
Key Skills:
- Bachelor's degree with 12+ years of professional experience or Master's degree with 10+ years of professional experience.
- Working knowledge on advance tech nodes 16ff and below is necessary
- Extensive knowledge and experience in back-end implementation tasks such as (timing & power), synthesis, low power implementation, power analysis, equivalence checking and STA.
- Experience at top-level will be added advantage.
- EDA tool knowledge on industry standard Synthesis, PnR, PV, FV, CLP, STA is a must.
- Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions and provide feedback to design team.
- Excellent written and verbal communication skills; ability to present complex issues with clarity to drive decisions
- Good control over scripting languages like PERL/TCL is MUST.
- Detail oriented, self-motivated team worker, good verbal and written communication skills.
- The candidate must have a minimum of 4 tape-out experience.
More information about NXP in India...
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