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Job Description Summary:

Hands on experience with 2.5/3DIC system planning, including exploration.

MSA – Si, Pi, Thermal and stress/fatigue analysis

Package design using Cadence APD, including IC package co-design.

Job Description:

We are looking for a highly skilled and motivated 3DIC Design Flow Engineer to implement system planning and integration of complex HPC and AI systems with chiplets. You will be responsible for developing and implementing advanced solutions for high-performance AI applications. This is a challenging and rewarding opportunity for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry. The engineer will design and implement 3DIC-compatible flows by collaborating with electronic design automation (EDA) tool developers, analog/digital/3DIC design teams, modeling teams, advanced packaging and 3DIC technology teams. The position requires expertise in System Design, 3DIC integration, and EDA tool enablement.

Responsibilities

• Develop 3DIC design flows compatible with multiple semiconductor foundries.
• Construct implementation and simulation methodologies for 3DIC designs.
• Collaborate with EDA developers  to enable and enhance tool features, building customized design scripts.
• Deliver flows optimized for large-scale GPU/SoC integration to support customer tape-outs.
• Work with cross-functional teams (3DIC, packaging, physical design, analog, digital, modeling, etc) to define specifications and requirements.
• Stay current with emerging trends in 3DIC to shape future design methodologies.

Required Skills

• BS in EE, CE or related equivalent with 5+ years of work experience or MS in EE, CE or equivalent with 3+ year of work experience
• Proven experience in System Planning.
• Strong knowledge of 3DIC design integration and flow development.
• Proficiency with Cadence/Synopsys/Ansys and other AMS/3DIC EDA tools (planning/integration, layout, simulation, extraction, validation).
• Strong analytical and problem-solving skills for design and CAD issues.
• Effective collaboration and communication skills across global teams.

Preferred Skills

• Programming skills in Python, Perl, SKILL, TCL, or Shell for design automation.
• Experience with Verilog/Verilog-A/AMS or other chip behavior modeling.
• Knowledge of PDN extraction, SI/PI, thermal, and reliability analysis (Totem, Voltus-Fi, Redhawk, Celsius, etc.).
• Exposure to API development for EDA tool integration.

The annual salary range for California is $101,500 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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