Cadence seeks a graduate intern to prototype algorithms that make ECO patches implementable, timing‑robust, and testable. Work spans timing‑aware ECO (slack preservation, CTS integrity, incremental P&R hints) and DFT ECO (scan stitching, lock‑up latches, ICG test‑enable consistency). Must be enrolled in a PhD or 2nd‑year MS with focus on VLSI CAD; strong C++/Python; experience in physical synthesis/DFT/formal equivalence preferred.