At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities

• Collaborate closely with foundry partners to understand process technology requirements and translate them into EDA tool enablement strategies.
• Provide technical guidance and support for foundry PDK development, validation, and deployment.
• Lead DTCO analysis and methodology development to optimize design rules, cell architectures, and process parameters for performance, power, and area (PPA).
• Develop and apply DTCO techniques to evaluate and improve standard cell libraries, SRAMs, and analog IPs.
• Perform design rule impact analysis and recommend modifications to improve manufacturability and design efficiency.
• Utilize DTCO-driven benchmarking to guide technology scaling decisions and design enablement strategies.
• Collaborate with process integration and device teams to align design methodologies with process capabilities.
• Support 3DIC design enablement including floorplanning, partitioning, interconnect modeling, and thermal analysis.
• Collaborate on EDA tool flows for TSV, interposer, and chiplet-based designs.
• Drive deployment and optimization of digital design flows including synthesis, place & route, timing analysis, power analysis, and signoff.
• Benchmark and validate EDA tools across process nodes and design styles.
• Provide hands-on support to foundry and design customers, resolving technical issues and ensuring successful tool adoption.
• Deliver training, documentation, and best practices to internal and external stakeholders.

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