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Job Description:

We are seeking a DFT (Design for Test) Architect & Implementation Engineer with expertise in designing and implementing DFT networks for SoC (System on Chip) devices with mixed  ASIC and  custom content. The ideal candidate will drive the DFT strategy, develop test methodologies, and work hands-on in integrating DFT features into the designs. This role requires deep knowledge of scan networks, scan insertion, boundary scan (JTAG), MBIST, ATPG, and fault coverage analysis.

Key Responsibilities:

DFT Architecture & Strategy:

• Define and develop DFT methodologies for ASIC designs to ensure high testability and fault coverage.
• Architect and implement scan, JTAG, and memory BIST (MBIST).
• Optimize DFT strategy to balance test coverage, performance, and area constraints.

Hands-On Implementation:

• Develop and integrate DFT structures such as scan networks, scan chains, boundary scan, MBIST, LBIST, and built-in self-test (BIST).
• Generate and verify ATPG (Automatic Test Pattern Generation) patterns for fault coverage analysis.
• Work with RTL design engineers to ensure DFT compliance in Verilog/VHDL-based designs.
• Run fault simulation, stuck-at and transition fault testing, and analyze coverage reports.

Collaboration & Validation:

• Work closely with RTL, synthesis, and physical design teams to ensure DFT design integrity.
• Collaborate with manufacturing and validation teams to implement test strategies for prototype bring-up.
• Debug and optimize DFT networks to achieve minimal test times.
• Work with EDA vendors to evaluate and integrate latest DFT tools and methodologies.

Requirements/Qualifications:

• 15+ years of experience in DFT architecture and implementation.
• Strong expertise in FPGA-based DFT methodologies (Xilinx, Intel/Altera, Lattice, etc.).
• Proficiency in Verilog/VHDL for FPGA design and test logic implementation.
• Hands-on experience with DFT tools (Synopsys DFT Compiler, Tessent, Mentor Tessent, Cadence Modus, or similar).
• Strong knowledge of JTAG (IEEE 1149.1, 1149.6), scan insertion, ATPG, MBIST, LBIST, and fault modeling.
• Experience in timing analysis and synthesis-aware DFT implementation.
• Familiarity with FPGA prototyping and board bring-up.
• Hands-on scripting skills in Python, TCL, Perl, or Shell for DFT automation.

Preferred Qualifications:

• Experience in AI/ML-driven DFT automation.
• Knowledge of high-speed interfaces and SERDES testing.
• Experience with post-silicon validation and ATE (Automated Test Equipment).
• Strong debugging skills using logic analyzers, oscilloscopes, and FPGA tools.

• Why Join Us?

• Work on cutting-edge FPGA-based designs for high-performance computing, automotive, or AI applications.
• Opportunity to architect and implement industry-leading DFT methodologies.
• Be part of a highly skilled team pushing the boundaries of FPGA design & test innovations.

Travel Time:

0% - 25%

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.