Job Details:

Job Description: 

About the Group
Design Technology Platform (DTP) is the heart for advanced process at Intel. Design Technology Platform (DTP) under TD must enable those technologies in design through design technology co-optimization (DTCO). You will work with design rule definition team, process team and PDK team for rule quality assurance, as well as helping rule development.

About the role

• You must fully understand the design rule intent from discussion and documents.

• To ensure rule quality you are responsible for test and capture the corner cases.

• There are approaches like pattern testing, script for sanity check, etc.

• You must have good communication skills to interact with cross teams.

• Apply your analytic methods to identify and solve the problems.

• We are looking for several design rule development and QA engineers that can fully develop, test, and release design rule QA collaterals.

• Support design rule formation and development.

• Align and standardize rule specification.

• Create and maintain test pattern by EDA tools you are familiar with.

• Develop and support complex algorithms for creating and manipulating layout design data.

• Understand layout of complex semiconductor devices.

• Execute the QA flow and regression.

• Create and manage specification documents. Build up QA flow and assessment mechanism.

• Verify your delivery with good coverage.

• Apply EDA tools to help for efficiency.

Qualifications:

Minimum Qualifications:

• Candidate must possess a MS degree or above in Electrical/Computer Engineering or related field. Experience in the following:

• Solid knowledge/experience of process and/or OPC and/or mask in advanced nodes.

• Strong knowledge of design layout structure and/or std. cell development.

• Experienced in working with design rule definitions.

• Experienced in quality assurance for design rule and/or design rule check.

• Industry standard CAD tools/flows for digital and/or analog design.

• Software development/programming in high-level languages (e.g. Python, C/C++, TCL, Perl).

• Experienced in implementation of high-level language compiler/interpreter.

• CAD tool scripting languages (e.g. Cadence SKILL) or equivalent tools.

• Demonstrate experience working on with UNIX and/or Linux platforms.

Preferred Qualifications:

• Demonstrate experience in DRC run set and algorithm development. Specific experience with Synopsys ICV and/or Siemens Calibre.

• Background of digital/analog/cell design.

• Good communication skills, willing to discuss with teams.

• Proven ability to analyze issues, solve problems, and bring closure.

          

Job Type:

College Grad

Shift:

Shift 1 (Taiwan)

Primary Location: 

Taiwan, Hsinchu

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.