Job Details:

Job Description: 

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications:

• The candidate must possess a BE/B.Tech, ME/M.Tech or Ph.D. degree in Electronics/Computer Engineering or Computer Science, with a thesis in the area of DFT, test CAD or formal verification.
• Candidate must have experience in following area :Logic and memory design principles, VLSI design flow and VLSI CAD algorithms. Tool, flows and methodology development for DFT insertion and test generation needs.
• Programming skills with one or more of the high level languages e.g. Verilog/C/C++/TCL/Perl/Python.
• Theoretical knowledge in computer science, including algorithms and data structures.
• Standard software engineering practices for version control, configuration management, debugging and validation.
• Preferred Qualifications:
  • Detailed understanding of logic and array design-for-test (DFT) principles and test CAD or formal verification algorithms;
  • knowledge of software design patterns and programming paradigms Linux OS features and scripting languages

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

India, Hyderabad

Business group:

Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.