Posted:
3/17/2025, 5:00:00 PM
Location(s):
Taipei, Taiwan
Experience Level(s):
Mid Level ⋅ Senior
Field(s):
Software Engineering
Workplace Type:
Hybrid
Senior engineer for ATE test software for available tester platforms, supporting latest Intel products development for CPU, graphics and Server products.
Owner of test methodology development, connect Design, DFT, Product Development Engineering, Test Engineering and ATE manufacturers such as Advantest and Teradyne to provide end to end testing solution
Education: BS in relevant field for study, and a minimum of 5 years of relevant industry experience.
Strong programming skills for writing and debugging test programs for Advantest V93K and ExaScale with SmarTest8 (Java) and Teradyne UFlex platforms, with hands on experience for VLSI HPC and SoC testing applications.
Experience with C++ and C# is preferred.
Experience cross multiple tester platforms is a plus.
Deep understanding of digital test fundamentals, in depth knowledge with fabrication process, design for test, yield analytics, Vmin/Fmax characterization, FA/FI and production manufacturing process.
Experience with modern x86 architecture, development of CP/FT test methods and test programs.
Familiar with at DFT implementations such as SCAN and MBIST.
Experience with protocol aware testing is a plus.
Support the team cross multiple Geo Locations, Fluent in both verbal and written English.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software