Posted:
7/31/2024, 5:00:00 PM
Location(s):
Timișoara, Romania
Experience Level(s):
Expert or higher ⋅ Senior
Field(s):
Software Engineering
Workplace Type:
Hybrid
Performs functional verification of IP logic to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Minimum Qualifications:
Bachelor's degree in Computer Science, Electronics Engineering, Mathematics, or a related field.
Proficiency with Object-Oriented Programming (OOP) concepts and languages such as C++ or Java.
Minimum of 10 years of experience in the verification domain, with hands-on experience in "e" (Specman) and/or SystemVerilog (SV) languages.
In-depth knowledge of UVM or similar verification methodologies, particularly the "e" flavor.
Assume ownership and lead the verification of large-scale ASIC designs, ensuring they meet architectural specifications.
Mentor junior verification engineers and provide technical leadership within the team.
Understanding of Digital Integrated Circuits and Hardware.
Description Languages (HDLs) like VHDL or Verilog.
Proficiency with Linux operating system.
Excellent communication skills and the ability to work effectively in a team environment.
Strong command of the English language, both written and spoken.
Preferred Qualifications:
Formal methodology knowledge.
GLS experience.
Experience with scripting tools and languages such as bash, csh, awk, Perl, or Python.
Familiarity with development tools like make and version control systems such as CVS or git.
Proven track record of debugging RTL failures and implementing corrective measures.
Work Model for this Role
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software