Posted:
3/31/2026, 12:05:26 PM
Location(s):
Oregon, United States ⋅ Phoenix, Arizona, United States ⋅ Hillsboro, Oregon, United States ⋅ Arizona, United States
Experience Level(s):
Mid Level ⋅ Senior
Field(s):
Product ⋅ UI/UX & Design
Workplace Type:
Hybrid
We're looking for a motivated, passionate, and talented Engineer to join Intel's Advanced Design Customer Enabling (ADCE) group within Assembly Packaging Technology manufacturing organization (APTM) to realize Intel's vision with advanced packaging technologies.
In this position, you will be responsible for defining Package and Disaggregation Architecture across Intel's product portfolios (CPUs, Chipsets, SOC designs and more) as part of the Advanced Design Group. The candidate will be responsible for working with the Si, Package and Board design teams to define and implement a co-design strategy which would optimize product performance and cost at the package and system level.
The job will require the candidate to understand silicon and packaging technology development FMEAs and product packaging requirements - both physical and electrical.
An ideal candidate would exhibit behavioral traits that indicate:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications:
Preferred Qualifications:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software