Sr Principal Digital Design Engineer (Backend)

Posted:
8/21/2024, 5:00:00 PM

Location(s):
Florida, United States

Experience Level(s):
Expert or higher ⋅ Senior

Field(s):
Software Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. 

 

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. 

 

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 

 

Job Title: Senior Principal Digital Design Engineer 

 

Location: Cork 

 

Reports to: Design Engineering Director 

 

Job Overview: 

The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. 

 

The Cadence IP Vision is to deliver industry leading IP solutions to enable our customers to be successful across these fast-moving application spaces. 

 

The Senior Principal Digital Design Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India. 

 

Job Responsibilities:

  • Understanding proper handling of multiple asynchronous clock domains and their crossings
  • Understanding of Lint checks and proper resolution of errors
  • Understanding of synthesis timing constraints, static timing analysis and constraint development
  • Understanding of fundamental physical design flows and stages
  • Candidate should be able to debug and contribute to DFT architectures for hard IP, soft IP, and integrated IP test chips.
  • Liaison between Controller, PHY and Test chip teams.
  • Technical leadership during the development of complex Ethernet IP development
  • Planning of activities and milestones for the Digital Controller Development teams.
  • Leadership of cross-functional technical meetings
  • Support customer pre-sales and post-sales meetings.
  • Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001.

Job Qualifications:

  • Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
  • 10-15 years’ experience in microelectronics/EDA industry.
  • In depth experience with Logic Synthesis, Static Timing Analysis and Constraints Development. 
  • Experience in Ethernet Systems, or other packet Protocol.
  • Experience in top-down and bottom-up digital design processes.
  • Experience of Verilog/System Verilog RTL Design
  • Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential.
  • Scripting Experience (Perl, TCL, Python)
  • Experience of Technical Team leadership essential.
  • Excellent oral and written English essential.
  • Self-motivated with excellent planning, interpersonal, and communication skills.

Additional Skills/Preferences:               

  • Experience of SoC Architecture and Development
  • Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
  • Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred.

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems

Website: https://www.cadence.com/

Headquarter Location: San Jose, California, United States

Employee Count: 5001-10000

Year Founded: 1988

IPO Status: Public

Industries: Aerospace ⋅ Electronic Design Automation (EDA) ⋅ Hardware ⋅ Mobile ⋅ Semiconductor ⋅ Software