Posted:
4/1/2026, 1:15:25 AM
Location(s):
Oregon, United States ⋅ Hillsboro, Oregon, United States
Experience Level(s):
Internship
Field(s):
Software Engineering
Workplace Type:
On-site
At Intel, Design Technology Platform (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Technology Platform (DTP)/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools. This position is for PDK Runset Development Intern, in the Design Technology Platform (DTP) organization. This internship will be for 6-9 months full-time.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must pursue a MS degree in Electrical/Computer Engineering, Computer Science, or a related field with experience in VLSI in Circuits and Digital Design
Candidate must have and maintain a 3.0 GPA or higher to be considered
Experience or coursework with Unix/Linux operating system
Experience or coursework with at least one of the following: C++, Python, Perl, TCL
Preferred Qualifications:
Experience with working in software repository management tools like Git
Experience with DRC/LVS/Extraction run sets and EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus, and simulation tools)
Experience with VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures
Experience with semiconductor device physics, models, parasitic extraction, and technology scaling
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $92,800.00-125,500.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Our standard internship rates are based on your degree, location, and the job role. Your recruiter can share more about the specific compensation range for your preferred location and job role during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software