Principal Software Engineer

Posted:
11/13/2025, 8:51:18 AM

Location(s):
San Jose, California, United States ⋅ California, United States

Experience Level(s):
Senior

Field(s):
Software Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the Role

We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows.

Key Responsibilities

  • Develop and optimize low-power verification software for Palladium and Protium platforms.
  • Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows).
  • Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
  • Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows:
    • AVIP + UPF + 2/4-state
    • UVMA + UPF + 2/4-state
    • MC + UPF
    • Dielets + UPF
  • Consolidate UPF software across Palladium and Protium platforms.
  • Support key initiatives such as:
    • MC+PPC flow with UPF 4-state
    • Compilation time optimization for UPF
    • Full Vision UPF probe integration
    • SAGE UPF debug with Verisium

Qualifications

  • Bachelor’s degree in Computer Science or Electrical Engineering with a minimum of 7 years of relevant experience,
    or Master’s degree with 5+ years of experience,
    or PhD with 1+ year of experience.

Required Skills

  • Strong proficiency in object-oriented design and C++ programming.
  • Experience with standard C/C++ libraries and the C++ Standard Template Library (STL).
  • Proven ability to develop high-performance software for large-scale data processing.
  • Scripting experience in Perl, Tcl/Tk, and/or Python.
  • Familiarity with IEEE 1801 standards and UPF implementation.
  • Experience with Verilog, SystemVerilog, and VHDL.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems

Website: https://www.cadence.com/

Headquarter Location: San Jose, California, United States

Employee Count: 5001-10000

Year Founded: 1988

IPO Status: Public

Industries: Aerospace ⋅ Electronic Design Automation (EDA) ⋅ Hardware ⋅ Mobile ⋅ Semiconductor ⋅ Software