Constraints and Conformal Architect

Posted:
12/13/2024, 11:31:55 PM

Location(s):
San Jose, California, United States ⋅ California, United States

Experience Level(s):
Expert or higher ⋅ Senior

Field(s):
Software Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Time type:  Full time

Job requisition id: ----

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an integral member of WFO, you work with the best-in-class EDA tools, collaborate with technical experts and work on advanced semiconductor chip designs in a dynamic, innovative environment focused on silicon design and design automation.  In this role you will provide engineering design services, for the most advanced Cadence customers. You will work with experienced Cadence design engineers to come up with innovative solutions to address our customers’ most challenging technical problems.

At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working with Cadence design engineers and customers, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design synthesis, LEC and low-power verification, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as a design Engineer here at Cadence will put your miles ahead in your career advancement.

Key Responsibilities:

  • Creation of design and timing constraints, at block and chip level.
  • Creation of hierarchical and flat timing constraints at chip level.
  • CDC and RDC Analysis and creation of related constraints and scripts
  • Provide help to PD and STA team on constraints, CDC, RDC
  • Formal equivalence check using LEC, including RTL to RTL, RTL to netlist
  • Analysis of power integrity of the design using CLP
  • Creation, implementation and maintenance of ECO flow
  • Conduct technical presentations and product demonstrations
  • Work closely with R&D to enhance the tools and methodologies to meet and exceed requirements of the project and customer
  • Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
  • Capture best practices and lessons learned from current projects and utilize it to improve efficiency and success rate in future projects 

Preferred Skills and Education

  • Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
  • 10+ years of industry Digital Design experience
  • A working knowledge of UNIX/Linux, C-shell, TCL/TK programming and scripting
  • A strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals and low power architectures
  • Strong Conformal LEC, Conformal Low-Power and Conformal ECO skills
  • Excellent verbal and written communication skills, fluency in English
  • Strong problem-solving skills
  • A team player who is passionate about technology and works well with both experienced and novice teammates
  • Experience in one and preferably more of the following disciplines:
    • Digital Circuit Design and verification (RTL design and verification)
    • Design and timing constraints - creation and verification
    • UPF - creation and verification
    • CAD support for Digital IC Design and related flows with focus on LEC, CLP verification and Conformal ECO
    • STA
  • Prior experience with Cadence tools such as Genus, Conformal, Tempus is highly desired
  • Experience with advanced nodes 7nm and below

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems

Website: https://www.cadence.com/

Headquarter Location: San Jose, California, United States

Employee Count: 5001-10000

Year Founded: 1988

IPO Status: Public

Industries: Aerospace ⋅ Electronic Design Automation (EDA) ⋅ Hardware ⋅ Mobile ⋅ Semiconductor ⋅ Software