NVIDIA's success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design.

We are seeking an innovative CAD Software Developer with particular interest in algorithms for gate-level timing and physical optimization, including sizing and buffering, clock skew, incremental place and route, and IR drop modeling. Understanding both software and hardware principles is key. Constant creativity and a self-drive to explore and perfect fast, high-capacity software is required. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, this is it! Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles.
 

What you’ll be doing:

• Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry's alternatives in high capacity timing closure and will advance even further with your contributions.

• Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, IR drop prediction, timing calculation, power minimization, ECO routing, and incremental parasitic extraction.

• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

• BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience

• Minimum 6+ years of relevant experience in CAD software and VLSI hardware design

• Strength in both CAD software and VLSI design

• Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.

• Demonstrated ability in software development using C++

• Familiarity with design implementation tools such as PrimeTime, Tempus, ICC2, Innovus, and StarRC and typical design flows written in Perl, Tcl, and Python.

• Strong communication and interpersonal skills

Ways to stand out from the crowd:

• C++14 or newer experience, such as lambdas and concurrency

• Advanced understanding of timing modeling or P&R algorithms, such as CCS models, moment matching, incremental routing, cell legalization, etc.

• Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.

NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!

The base salary range is 164,000 USD - 304,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.