Our opening is a technical role within the Engineering Automation (EA) organization at Micron! We deliver DTK (Design Technology Kit) collateral, environments, tools and flows for the design, implementation, verification, & tape out of custom memory designs! These CAD tools and collateral enable DRAM, NAND, and other emerging memory designs on a range of industry-leading Micron-developed process nodes.

Responsibilities:

• Perform day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to DRAM design teams. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells, automated place and route tools, physical design verification (LVS, DRC), ERC, Layout Parasitic Extraction, pre and post layout net listing and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis (including HCI, BTI, EM/IR), tape out and mask generation.
• Drive close collaboration with DRAM design, layout, &verification methodology teams to propose and co-develop capabilities outstanding or under supported by EDA vendors and deploy outstanding practices and methodologies consistently to DRAM designs worldwide.
• SPF/LVS tool and flow development including debugging, and support in collaboration with the CMOS Modeling team.

Qualifications:

The ideal candidate has the following qualifications:

• PhD, MS or BS in Computer Engineering, Computer Science or Electrical Engineering
• Open to new Ph.D. Graduate, Masters with 1+ years of relevant experience or Bachelors with 3+ years of relevant experience.
• SPF Extraction experience, supporting tools such as Siemens Star-RCXT or Cadence Quantus.
• Experience with HSPICE, Cadence Spectre, Primesim, or some other Analog simulator.
• Familiarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND).
• Knowledge of CMOS circuit design, layout and verification.
• CMOS transistor level design, logical design and net listing.
• Circuit simulation knowledge or experience including nanometer scale MOS and interconnect effects.
• Digital simulation and verification flows experience or knowledge (System Verilog/UVM test benches and coverage systems).