Posted:
1/2/2025, 4:00:00 PM
Location(s):
Ontario, Canada ⋅ Toronto, Ontario, Canada
Experience Level(s):
Senior
Field(s):
Software Engineering
Workplace Type:
Hybrid
The memory sub-system validation engineer is responsible to drive and deliver pre- and post-silicon validation and characterization of GDDR6/7 on Intel's ARC products. In this wide-ranging role, the validation engineer is the critical interface between DRAM architecture, Memory Controller Design, DDR PHY, DRAM product engineering, and software teams to ensure that advanced memory technologies are delivered from architecture to mass production. The validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
Responsibilities:
Memory sub-system validation engineer's responsibility includes planning, execution, and debug for pre- and post-silicon validation.
Develop and execute test plans for functional and electrical validation (PVT shmoo characterization).
Develop functional, electrical validation plans for memory features, align cross-functional teams on the support and validation plans
Drive debug in post silicon, root-cause problems and steer the team to the best corrective action to move forward
Collaborate and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware and Software
Professional traits:
The candidate possess knowledge of memory subsystem, including SoC memory architecture, memory controller, PHY design and high speed IO interface, DRAM device, and associated calibration/training mechanisms.
Proven ability to drive resolution of critical problems, while under pressure.
Able to work as a team and work efficiently in a dynamic environment and on multiple projects
Minimum qualifications
Preferred experience:
Annual Salary Range for jobs which could be performed in Canada
CAD 165,450.00-233,580.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.
Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software