CPU Performance Architect

Posted:
7/29/2024, 5:00:00 PM

Location(s):
Karnataka, India

Experience Level(s):
Junior ⋅ Mid Level ⋅ Senior

Field(s):
Software Engineering

Workplace Type:
Hybrid

Job Details:

Job Description: 

Be part of a SoC performance architecture team working on next generation client products. Research and improve methodologies and infrastructure for power and performance modeling, analysis and for workloads bring up, analysis. Own and drive research ideas to improve SoC power and performance including modeling these ideas in power and performance models and collaborating with wider arch and design teams to productize these ideas. Model proposed micro-arch in power and performance models, analyze bottle necks and propose solutions for them. . Work with validation teams to ensure power and performance features bring expected benefits in the product.

Qualifications:

Minimum Qualifications:

  • Computer arch expertise with courses/projects focusing on at least one aspect of computer architecture.
  • Alternately strong understanding of either traditional data structures and algorithms or deep learning techniques with an interest to apply them in computer architecture.
  • Under graduate/ graduate course in computer science or related fields with minimum.
  • 2 years experience in SoC performance modeling/analysis2. (or) Ph.D in computer science or related fields with specialization in computer architecture or allied fields Preferred.

Required Experience:

  • Experience with handling performance model/ performance analysis of complex SoCs with latency/ bandwidth/ power expectations
  • Expertise in specific sub-systems in SoC like caches, memory controller or fabrics.
  • Experience with performance modeling using C++/System C TLM
  • Exposure to any kind of scripting and RTL validation environments will be an added advantage.
  • Exposure to bringing up/integrating performance/functional simulators and/or analysis of workloads will also be an added advantage.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Intel

Website: https://www.intel.com/

Headquarter Location: Santa Clara, California, United States

Employee Count: 10001+

Year Founded: 1968

IPO Status: Public

Last Funding Type: Post-IPO Equity

Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software