Posted:
8/5/2024, 5:00:00 PM
Location(s):
Hillsboro, Oregon, United States ⋅ Oregon, United States ⋅ California, United States ⋅ Austin, Texas, United States ⋅ Texas, United States ⋅ San Jose, California, United States
Experience Level(s):
Expert or higher ⋅ Senior
Field(s):
Software Engineering
Workplace Type:
Hybrid
In Q4 2023, Intel® announced Altera will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel®. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future. Intel® Programmable Solutions Group (PSG) is looking for a SoC/Solution Micro-Architect for FPGA products. This forward-looking dynamic role provides unique opportunities to influence future product roadmap, requiring a self-starter with strong personal communication and collaboration skills.
As a SoC/Solution Micro-Architect, you will be responsible to work on feasibility of customer feature requests, partitioning them effectively between hardware/software and propose an effective implementation which meets the desired Power, Performance and Area targets. You will need to work with cross functional teams and will be responsible for defining Micro-architecture specifications for the FPGA solutions. You will also work closely with IP and platform implementation teams on the creation of Soft IP blocks, solutions and customer designs to enable those capabilities.
As a SoC Micro-Architect you will be responsible, but not limited to:
Define micro-architecture specifications.
Perform feasibility study on different third-party IP and integrate IP at the SOC level.
RTL Implementation, run Lint, CDC, Synthesis, STA and formal verification tools, work closely with Backend team on floorplan, Constraints definition and timing analysis.
Closely work with Verification team and help define test plan and debug design.
Participate in design reviews of hardware and related software systems.
Participate and drive timing convergence for high-speed designs including micro-architecture optimizations
Collaborate with internal and external team members on architectural decisions, development flows and methodologies.
Behavioral Traits
Excellent communication and documentation skill.
Must be skilled to influence in heavily matrixed environment.
Capable to operate in ambiguity where roles may not be clearly defined or teams across multiple/functions and IP/SOC must be pulled together.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Education Requirements:
Bachelor's degree in computer engineering, electrical Engineering or related field.
Minimum Qualifications
10+ years of relevant experience in the following areas:
Experience with IA or CPU based SoC designs processor based SoC architectures.
Experience with NoC design and integration with interconnect protocols, such as AXI, ACE, APB, etc.
RTL developer using ASIC development techniques and designs flows at modern technology nodes including synthesis and timing closure.
Digital Design experience
Preferred Requirements:
Master's degree in computer engineering, Electrical Engineering or related field.
6+ years of experience in the following areas:
Digital design involving multiple clock domains and clock power management.
Low power design, tools and methodologies. Power intent UPF specifications.
Experience with Ethernet, PCIe or TSN.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$162,041.00-$259,425.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software