At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs
• Timing analysis, validation and debug across multiple PVT conditions
• Run Tempus for STA flow optimization and Spice to STA correlation.

• Required Skills -

• Educational Qualification: MS/MTech/BE/ BTech  in Electronics from reputed institutes with 2 + years experience
• Physical design experience in ASIC design environment
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
• Hands-on experience with STA tools - Prime-time, Tempus
• Have experience working on timing convergence at Chip-level and Hard-Macro level.
• In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
• A strong grasp of ML fundamentals
• Should have excellent leadership, communication, analytical and problem solving skills
• Should be self-motivated and good team player
• Evaluate multiple timing methodologies/tools on different designs and technology nodes
• Work closely with RnD to explore Agentic AI capabilities to improve design efficiency. 
• Development, automation and maintenance of EDA flows and scripts for physical implementation
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
• Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
• Solid scripting skills including Python and Tcl.

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