Sr./Principal HBM CAD Engineer - TPG

Posted:
11/20/2024, 2:51:07 AM

Location(s):
Richardson, Texas, United States ⋅ Folsom, California, United States ⋅ California, United States ⋅ Texas, United States

Experience Level(s):
Senior

Field(s):
Mechanical Engineering

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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

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The Senior/Principal HBM CAD Engineer is a technical leadership role within the Engineering Automation (EA) organization at Micron. We deliver DTK (Design Technology Kit) collateral, environments, tools and flows for the design, implementation, verification, & tape out of custom memory designs. These CAD tools and collateral enable DRAM, NAND, and other emerging memory designs on a range of industry-leading Micron-developed process nodes.

Specific focus:

TSMC mixed-signal, custom-digital experience like ADE-XL, Spectre, synthesis tools (DC/Genus), implementation tools (ICC2, Innovus), STA (Primetime, Tempus), EMIR (Redhawk, Voltus etc), functional & timing verification of cell-based designs (dynamic simulation and static analysis). Our ideal candidates combine pure digital RTL2GDS blocks with custom digital & analog blocks using TSMC collateral/environments for high speed, low power, area-efficient designs.

Responsibilities:

  • Own the day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to HBM design teams at the Dallas or Folsom Design Center. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells, automated place and route tools, physical design verification (LVS, DRC), ERC, Layout Parasitic Extraction, pre and post layout net listing and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis (including HCI, BTI, EM/IR), tape out and mask generation.
  • Drive close collaboration with HBM design, layout, & verification methodology teams to propose and co-develop capabilities outstanding or under supported by EDA vendors and deploy outstanding practices and methodologies consistently to High Bandwidth Memory designs worldwide.
  • Drive research and development at the intersection of IC Design Automation and Machine Learning to envision, scope, develop and deliver solutions benefiting IC design.

Qualifications:

  • Bachelor or preferably Masters/PhD in Computer Engineering, Computer Science or Electrical Engineering
  • (5-15) + years of direct CAD or Design experience in mixed-signal, custom IC design flows or Digital RTL to GDS Flows.
  • Familiarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND)
  • Knowledge of CMOS circuit design, layout and verification, and in-depth experience supporting some of these areas:
  • CMOS transistor level design, logical design and net listing CMOS digital and analog layout, Cadence Skill, and parameterized cells
  • Automated place and route tools
  • LVS, DRC, LPE flows
  • ERC flows, static and dynamic circuit checks
  • Circuit simulation including nanometer scale MOS and interconnect effects
  • Digital simulation and verification flows (System Verilog/UVM test benches and coverage systems)
  • Power delivery network simulation and analysis
  • Reliability flows such as HCI, BTI, EM/IR, crosstalk
  • Mask generation and tape out basics
  • Knowledge and experience vetting and deploying sophisticated EDA software flows
  • Experience qualifying vendor tools and internally developed software releases
  • Experience developing software prototypes for innovative ideas in IC design, layout, and analysis
  • Experience running agile (software) sprints is a plus
  • Experience with Machine Learning algorithms and applications
  • Experience and record of accomplishment delivering production-grade ML applications in IC Design (one or more areas including custom design, layout, logic and timing verification, circuit simulation and physical design verification)
  • Excellent communication and problem-solving skills are required
  • Strive to continuously learn, develop new skills, and self-improve

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$100,000.00 - $253,500.00

Our salary ranges are determined by role, level, and location.  The range displayed on each job posting reflects the minimum and maximum target for new hire salaries of the position across all US locations.  Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training.  The pay scale is subject to change depending on business needs.  Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Additional compensation may include benefits, discretionary bonuses and equity.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.  We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.  Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.  Additionally, Micron benefits include a robust paid time-off program and paid holidays.  For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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