Responsible for writing high performance code and verifying the performance against hardware for deep learning and AI workloads. Run benchmarks or key customer workloads under simulation to identify performance bottlenecks and optimize them. Debug and optimize compiler back-ends for the RISC-V architecture. Collaborate cross-functionally with Silicon design, architecture experts, and other teams across the company. Develop drivers for various IP blocks in embedded environments and in the Linux kernel for the development boards using lab equipment. Work with the silicon team to craft specifications for the future product chips and build software to run on the chips and boards. Create and maintain CI for the existing repos used by the software team.
Worksite: 3315 Scott Blvd, Fl 4, Santa Clara, CA 95054
Applicant Instructions: Include job code 91839 in application. EOE