Posted:
1/26/2025, 4:00:00 PM
Location(s):
Penang, Malaysia ⋅ George Town, Penang, Malaysia
Experience Level(s):
Mid Level ⋅ Senior
Field(s):
Product
Workplace Type:
Hybrid
In this position, the candidate will engage in the structural design or design automation of SOC design blocks in advanced process nodes using latest Tools, Flow, Methodology.
Your responsibilities will include but not be limited to:
- Perform structural design and implementation in logic synthesis, placement, clock tree synthesis, routing and design sign-off (PV, LV and RV) in advanced process nodes from Intel and other foundries.
- Work with the tools, flows and methodology (TFM) team to drive the most competitive Electronic Design Automation (EDA) solutions and methodology in advanced process nodes from Intel and other foundries.
- Perform BE TFM validation on production project config with real SOC design block.
- Develop TFM Validation concepts and methodology (software testing practice, test management, test case/design development and QA flow automation)
- Work with global development teams to develop design recipes and solutions needed to deliver the most competitive solutions for our internal customers.
- Lead junior engineers in all the above areas
� Bachelor or Master degree in relevant fields with hands-on experience in SoC development projects
� Basic understanding of SoC design methodologies, design flows, and design collateral
� Experience in developing design automation solutions/scripts using Python, Perl or TCL to automate a wide variety of designs
� Experience in implementing design blocks from RTL to Layout and design sign-off
� Knowledge and experience in using any EDA tools such as Fusion Compiler and/or Genus-Innovus
� Strong analytical and debugging skills. Excellent communication and interpersonal skills
� Ability to work effectively with global teams in a variety of geographies
� Excellent communication skills with an ability to synthesize complex info into easy to digest form for senior executives
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software