Posted:
2/20/2026, 4:39:19 AM
Location(s):
Texas, United States ⋅ California, United States ⋅ Folsom, California, United States ⋅ Austin, Texas, United States ⋅ Santa Clara, California, United States ⋅ Oregon, United States ⋅ Hillsboro, Oregon, United States
Experience Level(s):
Mid Level ⋅ Senior
Field(s):
Software Engineering
Workplace Type:
Hybrid
Are you passionate about advancing the future of hardware design through cutting-edge tools and methodologies? Join our dynamic team as a Hardware Design Tools and Methodology Engineer, where you'll play a pivotal role in designing, implementing, verifying, and supporting the enablement and adoption of revolutionary hardware design tools, flows, and methodologies. This is your opportunity to work at the forefront of technology innovation, collaborating with industry leaders to shape the next generation of design automation solutions.
Why Join Us? This is your chance to be part of a team that's revolutionizing hardware design methodologies and making a global impact on technology development. You'll work with cutting-edge tools, collaborate with industry experts, and contribute to innovations that shape the future of semiconductor design.
Ready to drive the future of hardware design automation? Apply now and join our mission to create extraordinary design solutions!
Key Responsibilities:
Design and Implementation Excellence:
Design, implement, verify, and support the enablement and adoption of advanced hardware design tools, flows, and methodologies
Define comprehensive methodologies for hardware development related to technology nodes and EDA tool enabling
Create and verify unique hardware designs, assemble design platforms, and integrate components into hierarchical systems
Technology Innovation:
Provide deployment coverage for end-to-end EDA tool testing on new technology nodes
Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance
Support development and enhancement of platforms, databases, scripts, and tool flows for design automation
Technical Leadership:
Build deep understanding of digital design, verification, structural and physical layout, fullchip integration, power and performance, clocking, and/or timing to enhance future TFM development
Collaborate with EDA vendors on defining and early testing of next-generation design tools
Specialized Focus Areas: In this role, you will be responsible for developing:
Extraction Runset development
Extraction tool/flow certification on Intel's process technologies
Work collaboratively with technology specification owners and validation teams to ensure high-quality solutions
Frequent interaction with Process Development Teams and EDA vendors to enable production-level extraction solutions
Minimum Qualifications:
Bachelor's Degree with 8+ years, OR Master's Degree with 5+ years, OR PhD with 3+ years of experience in Physics, Electrical & Computer Engineering, or related field
3+ years of experience in one of the following skill sets:
LVS/Extraction Runset Development in ICV PXL or Calibre SVRF or Pegasus language
StarRC or Quantus, or xACT based extraction flows, methodologies and/or certification
Scripting knowledge in TCL, Perl, or Python
Preferred Qualifications:
2+ years of experience in Physical Verification/DRC/LVS/PEX/TVF
2+ years of working in Unix/Linux operating system environment
1+ year of experience in 3D IC Extraction (SNPS VIB, or Cadence IDX) flow
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software