Job Details:

Job Description: 

This position is within the Design Technology Platform (DTP) organization. The Runset Development team within this organization is looking for talented individuals to develop physical layout verification software (DRC, LVS, RC extraction) and support the latest Intel technologies and microprocessor designs.

At Intel, Design Technology Platform is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies.

As part of the Process Design Kit (PDK) group in DTP, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers.

The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.

Responsibilities include but not limited to:

• Develop physical layout verification design rule checker (DRC), Layout vs Schematic (LVS), and RC extraction runsets using industry standard EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)
• Work with the process development teams at Intel to define specifications for DRC, LVS, and RC extraction runsets
• Coordinate development of technology features, develop QA plans, and drive test-cases development working with relevant stakeholders
• Support PDK development and Intel design teams to debug and enhance runset quality and enhance runtime and usability of the runsets
• Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification
• Assess architecture and hardware limitations, plans technical projects in the design and development of CAD software
• Help library teams at Intel with technology path finding activities

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor of Science in Computer Engineering (CE), Electrical Engineering (EE) with 5+ years of semiconductor industry experience OR Master of Science in CE, EE with 4+ years of semiconductor industry experience.

Required semiconductor industry experience in the following areas:

• DRC or LVS runsets development in any one of the EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)
• Unix/Linux operating system
• At least one of the following: C++, Python, Perl, TCL
• At least one of the following: VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures

Preferred Qualifications:

• Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling
• Experience with working in software repository management tools like Git

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.