Job Details:

Job Description: 

Do Something Wonderful
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Intel's Foundry Technology Development Design Technology Platform (TD DTP) group is looking for a design rule verification engineer who will collaborate with design rule definition team, process team and PDK team for design rule development and verification.
On-site presence is not required. Remote or Hybrid work modes are supported.

Major Duties and Responsibilities Include:

• Thoroughly understand the design rule intent through discussions and documentations. Candidate should have effective verbal or written communication and analytical problem solving and troubleshooting skills in design rule development.

• You will utilize modern design rule development methodologies, programming languages, domain knowledge, test, and release design rule QA collaterals. Facilitate the development and improvement of design rules, ensuring alignment and standardization of rule specifications.

• Analyze design rule correlation and dependency, conduct coding assessment and release example DRC runset by identifying and testing corner cases to ensure the PDK quality and performance.

• Develop and maintain a comprehensive QA flow and assessment mechanism. Ensure through verification of deliverables to achieve extensive coverage.

• Implement the QA flow and conduct regression testing. Develop and maintain specification documents.

Qualifications:

Minimum Qualifications

• Candidate must possess a BS degree with 1+ years of experience or an MS degree in Computer Science, Computer Engineering, Electrical Engineering, or related discipline.

• Software programming skills in Python, Perl or, TCL.

• Effective communication skills, willing to discuss with teams.

Preferred Qualifications

• 3+ months of semiconductor industry experience.

• 3+ months experience with Unix/Linux operating system.

• Proven ability of issue analysis, problem solving, and bring closure.

• Industry standard CAD tools/flows for digital and/or analog design.

• CAD tool scripting languages. (e.g. Calibre DESIGNrev, Cadence SKILL)

• Minimum of 1 year of experience in DRC runset development using any of the following EDA tools:

-Siemens Calibre

-Synopsys ICV

-Cadence Pegasus

          

Job Type:

College Grad

Shift:

Shift 1 (Taiwan)

Primary Location: 

Taiwan, Hsinchu

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.