Posted:
4/1/2026, 7:58:53 AM
Location(s):
California, United States ⋅ Santa Clara, California, United States
Experience Level(s):
Junior ⋅ Mid Level ⋅ Senior
Field(s):
Software Engineering
Workplace Type:
Hybrid
We are seeking a motivated entry-level System Software Engineer to support semiconductor chip design workflow optimization, high-performance computing infrastructure, and AIOps automation. The ideal candidate will have hands-on experience with EDA toolsets and chip design flows, AI application development, Infrastructure as Code (IaC) automation, and a solid understanding of security technologies and authentication protocols (LDAP, Kerberos, etc.).
Key Responsibilities
Assist in identifying design flow performance bottlenecks and resource inefficiencies and drive targeted workflow optimizations.
Engage in data center infrastructure software development lifecycle (SDLC) and operations management, proactively identifying AIOps transformation opportunities and executing automation initiatives to drive operational efficiency improvements.
Work with senior engineers in next generation to identify and access Management (IAM) solution development, including migration from legacy NIS systems to modern LDAP and Active Directory backend infrastructure.
Minimum Qualifications
Bachelor's degree in Computer Science, Electrical Engineering, or related specialized field.
Advanced knowledge of Linux / Unix systems.
Experience in Python, C++, Java, Shell scripting, SQL.
Experience version control systems (Git, Perforce).
Hands-on experience with AI/ML, NLP, data analysis, AI software frameworks (TensorFlow, PyTorch, or similar tools).
IAM and authentication protocols / mechanisms (LDAP, Kerberos, WMI, etc.) experience.
Preferred Qualifications
Internship or project experience in semiconductor space and knowledge of semiconductor design processes.
Software licensing management (FlexLM) experience.
Experience with high-performance computing clusters and job scheduling systems.
IP protection and confidentiality requirements in chip design experience.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $95,640.00-156,740.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software