Posted:
7/22/2025, 5:00:00 PM
Location(s):
San José, San Jose Province, Costa Rica ⋅ San Jose Province, Costa Rica
Experience Level(s):
Entry Level/New Grad ⋅ Junior ⋅ Mid Level
Field(s):
IT & Security
Workplace Type:
On-site
The Foundational Security team (FST) is looking for digital logic designers and validators keen to work on a scalable IP design.
The candidate will have an opportunity to learn and contribute towards making Intel Hardware more secure.
The primary responsibilities for this role will include, but are not limited to:
Candidate will be responsible for design and validation of new IP roadmap features as part of FST's HW IP developing HW security for various market segments across Intel.
As a member of the team, the candidate would be responsible for driving scalable IP development while also making the Design Integration and SOC delivery a fully automated solution.
The candidate will be part of an IP team working closely with other verification engineers, RTL design engineers, micro-architects, and other team members in determining the proper implementation strategy for new design, ensure quality of design, and develop test-plans, verification environment, and drive delivery to SoC.
A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
Strong analysis.
Debugging skills.
Creative in problem solving.
Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical skills, along with having passion for design or validation.
Must have strong orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies and have strong strategic thinking to come up w/ paradigm shift solutions to critical design/validation challenges.
Minimum Qualifications:
Minimum qualifications are required to be initially considered for this position.
Candidate must be pursuing a BS degree in Electronic, Electrical, Mechatronic engineer, computer science, or related STEM field.
6+ month experience in Very Large-Scale Integration (VLSI).
Willing to remain at least 1 year as an active student.
Willing to work at least 30 hours per week
Intermediate to advanced English Level.
Costa Rican unrestricted work permit.
Preferred Qualifications:
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Knowledge in any of the next areas is a plus:
System Verilog / OOP, OVM/UVM.
IP-level design and/or verification.
SOC-level design/integration and/or validation.
RTL quality checks.
Simulation-based debug (VCS, Verdi, DVE).
Computer (CPU) and/or System (Platform) Architecture.
Emulation at SoC and/or Platform level.
Firmware and/or boot development/debug.
Python programming.
Front-end Design TFMs (Tools, Flows, and Methodologies).
Relevant experience can be obtained through schoolwork, classes and project work, internships, and/or work experience.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.Website: https://www.intel.com/
Headquarter Location: Santa Clara, California, United States
Employee Count: 10001+
Year Founded: 1968
IPO Status: Public
Last Funding Type: Post-IPO Equity
Industries: Artificial Intelligence (AI) ⋅ Information Technology ⋅ Product Design ⋅ Semiconductor ⋅ Software