Job Description

The Senior/Principal CAD Engineer - Parasitic Extraction is a technical role within the Engineering Automation (EA) organization at Micron! We deliver DTK (Design Technology Kit) collateral, environments, tools and flows for the design, implementation, verification, and tape out of custom memory designs. What we develop helps enable DRAM, NAND, and other emerging memory designs on various industry-leading Micron-developed process nodes!

Responsibilities:

• Perform day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to DRAM design teams. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells, automated place and route tools, physical design verification (LVS, DRC), ERC, Layout Parasitic Extraction, pre and post layout netlisting and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis (including HCI, BTI, EM/IR), tape out and mask generation.
• Drive close collaboration with DRAM design, layout, and verification methodology teams to propose and co-develop capabilities outstanding or under supported by EDA vendors and deploy outstanding practices and methodologies consistently to DRAM designs worldwide.
• SPF/LVS tool and flow development including debugging, and support in collaboration with the CMOS Modeling team.

Qualifications:

The ideal candidate has the following qualifications:

• PhD, MS or BS in Computer Engineering, Computer Science or Electrical Engineering
• 8 + years of direct CAD or Design experience in mixed-signal, custom IC design flows
• SPF Extraction experience, supporting tools such as Synopsys Star-RCXT, Siemens/Mentor Grapics PEX or Cadence Quantus.
• Calibre LVS rule development and tool support experience is highly preferred
• CMOS ITF and interconnect Modeling experience
• Experience working in highly technical IC Design or CAD teams distributed worldwide
• Familiarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND)
• Knowledge of CMOS devices, circuit design, layout and verification, and in-depth experience supporting extraction flows.
• Knowledge and experience in vetting and deploying sophisticated EDA software flows
• Experience qualifying vendor tools and internally developed software releases
• Experience developing software prototypes for innovative ideas in IC design, layout, and analysis
• Experience with Machine Learning algorithms and applications
• Excellent communication and problem-solving skills are required
• Strive to continuously learn, develop new skills, and self-improve