In an environment of continuous growth and new microcontroller product development, we are seeking to strengthen our Physical Design team. Our mission is to transform functional hardware descriptions into highly reliable MCU SoCs.

Starting from RTL descriptions and MCU specific requirements—including clocking concepts, peripheral integration, low power modes, mixed signal interfaces, and test methodologies—our team creates optimized physical implementations for SoCs. This includes library selection, transformation of RTL functionality into structural components, physical distribution within the SoC floorplan, and validation of timing, and power.

We work closely with Frontend Design, Analog, DFT, and Package/Assembly  to ensure smooth integration of the MCU architecture.

In your new role, you will participate in the physical implementation of complete MCU SoCs. Starting with synthesis there will follow placement, clock tree and DFT insertion, routing, and timing analysis.

The ideal candidate should have skills in one or more of the following areas:

• RTL-to-Gate Level synthesis
• Constraining of circuit timing
• Interface to design front-end to review constraints, suggest RTL changes in timing-critical paths,
• Static Timing Analysis (STA)
• Implement and analyze clock trees.
• Optimization for low power consumption
• Floor-planning and manual layout knowledge
• Analysis of signal integrity and IR drop, fix issues
• TCL, Pearl, or Python knowledge
• Experience with UNIX / Linux environment

Requirements:

• Bachelor or Master degree in Electrical Engineering or similar
• Fluent in English and the ability to work within international teams
• Practical experience in chip design or CAD
• Excellent communication and presentation skills across various levels and functions.
• Collaborative skills for working efficiently in a team having worldwide connections with partners and users.

More information about NXP in Germany...

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