At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design and develop cycle approximate/Loosly timed C++/SystemC models for Cadence's IPs like PCIe controller, etc for use in early SW development ,architectural exploration and performance analysis at different levels - subsystem and SoC level.

- Design and develop protocol specific functional models for various Cadence's interface IPs like PCIe,UCIe,CXL,USB,Ethernet,UFS,DP, etc

- Interact with IP designers and architects to understand various IP design/implementation specification and behavior

- Participate in defining traffic patterns, tools and methodology based on the model to help identify functional issues and performance bottlenecks

- Documentation of design specifications, implementation details, FAQ's, application notes, etc

Experience in high performance SOC architecture with focus on system-level trade-offs

                - Development of functional and behavioral (loosly timed)/(cycle-level) models using C++/SystemC/TLM2

                - Experience in using RTL/UVM System Verilog simulation environments for model validation       

                - Experience in creating workloads for different SoC components at required levels of abstraction

                - Knowledge of scripting languages (python, perl)

                - Excellent communication skills and ability to work in a team spread over multiple time-zones

               - BS/MS degree in Computer Science or Electrical Engineering, or equivalent practical experience(2-3yrs)

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