Location(s): Telangana, India ⋅ Hyderabad, Telangana, India
Experience Level(s): Junior
Field(s): Software Engineering
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Work with RnD on developing and pioneering "Agentic AI" capabilities to optimize PPA for IP’s and Soft Controllers to have the best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries.
Development, automation and maintenance of EDA flows and scripts for physical implementation
Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
Required skills –
Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years experience
Physical design experience in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
A strong grasp of ML fundamentals
Should have excellent leadership, communication, analytical and problem solving skills
Should be self-motivated and good team player
Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
Solid scripting skills including Python and Tcl.
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