From-scratch development of IP or SoC testbenches; Ownership of complete verification cycle (verification planning -> coverage closure) in a project; Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements; Integration of 3rd party VIPs

Required Qualifications

System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills.

Preferred Qualifications

• From-scratch development of IP or SoC testbenches
• Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262)
• Background with power-ware (UPF) and gate-level simulations (GLS)
• Ownership of complete verification cycle (verification planning -> coverage closure) in a project
• Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements
• Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs