Front End ASIC RTL/Logic Verification Engineer

Posted:
4/28/2026, 10:44:28 PM

Location(s):
Penang, Malaysia

Experience Level(s):
Junior ⋅ Mid Level ⋅ Senior

Field(s):
Software Engineering

Workplace Type:
On-site

Pay:
$147k–$245k/yr

Job Details:

Job Description:

  • Develops the verification plan to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

  • Supports SoC customers to ensure high-quality integration and verification of the IP block.

  • Drives quality assurance compliance for smooth IP-SoC handoff.

Qualifications:

• BS/MS or PhD in Electronics Engineering

• Strong in communication, leadership, investigation, problem solving & analytical skill

• Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments

• Knowledge of scripting is an advantage

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.