Job Details:

Job Description: 

This position is within the Design Enablement (DE) organization of Intel Technology Development group. We are looking for a talented individual to join DE MY TestChip Design team to evaluate Intel advanced process nodes using both in-house and external digital IPs. Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. #designenablement

Qualifications:

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor Degree (Master Degree preferred) in Electrical Engineering, Computer Engineering, Computer Science, or other related field of study. 1 years of relevant experience in silicon design and/or TFM development Experience in the following areas: - Scripting skills using a programming language such as Perl, TCL, or Python - Use of industry standard placement and routing CAD tools Preferred: - Floor planning and power grid setup, Clock methodologies, IR droop and SI mitigation strategies, power and timing signoff conditions, and layout and reliability verification. - VLSI circuits, design techniques, and sub-micron CMOS technologies - Logic synthesis and automated place and route tools - Logic equivalent verification debugging - Logic design fundamentals #designenablement

          

Job Type:

College Grad

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.